SWMR32 MC68HC908MR32 software examples

mr_regs.inc save this file in the same direction as the asm-file

PTA    EQU $0000     ; Ports and data direction
PORTA  EQU $0000
PTB    EQU $0001
PORTB  EQU $0001
PTC    EQU $0002
PORTC  EQU $0002
PTD    EQU $0003
PORTD  EQU $0003
DDRA   EQU $0004
DDRB   EQU $0005
DDRC   EQU $0006
DDRD   EQU $0007
PTE    EQU $0008
PORTE  EQU $0008
PTF    EQU $0009
PORTF  EQU $0009
DDRE   EQU $000C
DDRF   EQU $000D

TASC    EQU $000E    ; Timer A
TACNTH  EQU $000F
TACNTL  EQU $0010
TAMODH  EQU $0011
TAMODL  EQU $0012
TASC0   EQU $0013
TACH0H  EQU $0014
TACH0L  EQU $0015
TASC1   EQU $0016
TACH1H  EQU $0017
TACH1L  EQU $0018
TASC2   EQU $0019
TACH2H  EQU $001A
TACH2L  EQU $001B
TASC3   EQU $001C
TACH3H  EQU $001D
TACH3L  EQU $001E

CONFIG  EQU $001F    ; System configuration

PCTL1   EQU $0020    ; Pulse width modulator
PCTL2   EQU $0021
FCR     EQU $0022
FSR     EQU $0023
FTACK   EQU $0024
PWMOUT  EQU $0025
PCNTH   EQU $0026
PCNTL   EQU $0027
PMODH   EQU $0028
PMODL   EQU $0029
PVAL1H  EQU $002A
PVAL1L  EQU $002B
PVAL2H  EQU $002C
PVAL2L  EQU $002D
PVAL3H  EQU $002E
PVAL3L  EQU $002F
PVAL4H  EQU $0030
PVAL4L  EQU $0031
PVAL5H  EQU $0032
PVAL5L  EQU $0033
PVAL6H  EQU $0034
PVAL6L  EQU $0035
DEADTM  EQU $0036
DISMAP  EQU $0037

SCC1    EQU $0038    ; SCI (Asyncronous communications)
SCC2    EQU $0039
SCC3    EQU $003A
SCS1    EQU $003B
SCS2    EQU $003C
SCDR    EQU $003D
SCBR    EQU $003E

INTSCR  EQU $003F    ; IRQ status/control
ISCR    EQU $003F

ADSCR   EQU $0040    ; A to D converter
ADRH    EQU $0041
ADRL    EQU $0042
ADCLK   EQU $0043

SPCR    EQU $0044    ; SPI (Syncronous communications)
SPSCR   EQU $0045
SPDR    EQU $0046

TBSC    EQU $0051    ; Timer B
TBCNTH  EQU $0052
TBCNTL  EQU $0053
TBMODH  EQU $0054
TBMODL  EQU $0055
TBSC0   EQU $0056
TBCH0H  EQU $0057
TBCH0L  EQU $0058
TBSC1   EQU $0059
TBCH1H  EQU $005A
TBCH1L  EQU $005B

PCTL    EQU $005C    ; Clock Generator Module
PBWC    EQU $005D
PPG     EQU $005E

SBSR    EQU $FE00    ; System integration
SRSR    EQU $FE01
SBFCR   EQU $FE03

FLCR    EQU $FE08

BRKH    EQU $FE0C    ; Hardware breakpoint
BRKL    EQU $FE0D
BRKSCR  EQU $FE0E

LVISR   EQU $FE0C    ; Low voltage detect
FLBPR   EQU $FF7E    ; Flash boot protect

COPCTL  EQU $FFFF    ; COP (Computer operating properly) control

Decimal counter output on PORTB

CONFIG  EQU  $001F
PORTB   EQU  $0001
DDRB    EQU  $0005


                ORG     $8000

START           mov     #$01,CONFIG     ; disable COP
                mov     #$FF,PORTB
                mov     #$FF,DDRB
                clra

LOOP            inca
                cmpa    #10T            ; T -> decimal
                blo     WRITE_PORTB
                clra
WRITE_PORTB     sta     PORTB

                ldhx    #60000T          ; delay time
next_x1         aix     #-1
                cphx    #0T    
                bne     next_x1

                ldhx    #60000T          ; delay time
next_x2         aix     #-1
                cphx    #0T    
                bne     next_x2

                JMP     LOOP

                ORG     $FFFE
                dw      START           ; Reset vector

flashing lights left

CONFIG  EQU  $001F
PORTB   EQU  $0001
DDRB    EQU  $0005


                ORG     $8000

START           mov     #$01,CONFIG     ; disable COP
                mov     #$FF,DDRB
                mov     #$01,PORTB

LOOP            ldhx    #60000T
next_delay      aix     #-1
                cphx    #0
                bne     next_delay

                lsl     PORTB
                tst     PORTB
                bne     SHIFT_OKAY
                mov     #$01,PORTB
SHIFT_OKAY

                JMP     LOOP

                ORG     $FFFE
                dw      START           ; Reset vector

flashing lights right

CONFIG  EQU  $001F
PORTB   EQU  $0001
DDRB    EQU  $0005

                ORG     $8000

START           mov     #$01,CONFIG     ; disable COP
                mov     #$FF,DDRB
                mov     #$80,PORTB

LOOP            ldhx    #60000T
next_delay      aix     #-1
                cphx    #0
                bne     next_delay

                lsr     PORTB
                tst     PORTB
                bne     SHIFT_OKAY
                mov     #$80,PORTB
SHIFT_OKAY
                JMP     LOOP

                ORG     $FFFE
                dw      START           ; Reset vector

flashing lights runs from left to right and back

CONFIG  EQU  $001F
PORTB   EQU  $0001
DDRB    EQU  $0005

                ORG     $60
direction       ds      1

                ORG     $8000

START           mov     #$01,CONFIG     ; disable COP
                mov     #$FF,DDRB
                mov     #$01,PORTB
                mov     #$0,direction

LOOP            ldhx    #60000T
next_delay      aix     #-1
                cphx    #0
                bne     next_delay

                tst     direction
                bne     GO_RIGHT
                lsl     PORTB
                tst     PORTB
                bne     SHIFT_OKAY
                mov     #$80,PORTB
                mov     #1,direction
                bra     SHIFT_OKAY

GO_RIGHT        lsr     PORTB
                tst     PORTB
                bne     SHIFT_OKAY
                mov     #$01,PORTB
                mov     #0,direction

SHIFT_OKAY
                JMP     LOOP

                ORG     $FFFE
                dw      START           ; Reset vector

TIMER CONTROL COMPARE FUNCTION

we initialize TIMER B and set only the compare function

****************************************
** Register **
$include        'mr_regs.inc'


        ORG     $F000
START   RSP
        MOV     #$01,CONFIG
        MOV     #$FF,DDRB
        MOV     #$AA,PORTB
        MOV     #$30,TBSC       ; stop Timer to make changes
        MOV     #$10,TBSC0      ; only compare
        MOV     #$00,TBSC       ; start Timer


LOOP    lda     TBSC0
        bpl     LOOP		; wait until BIT7 is set 
        bclr    7,TBSC0
        lda     PORTB           ; on PORTB 18.76 Hz
        eor     #$FF
        sta     PORTB

        jmp     LOOP


********* Reset vector *********************
        ORG     $FFFE
        dw      START

TIMER_A COMPARE with TOGGLE OUTPUT 1KHz

TimerA The compare function with output toggle is set

****************************************
** Register **
$include        'mr_regs.inc'

        ORG     $F000
START   RSP
        MOV     #$01,CONFIG
        MOV     #$FF,DDRB
        MOV     #$AA,PORTB
        MOV     #$30,TASC       ; stop Timer to make changes
        MOV     #$14,TASC0      ; compare with toggle 
        MOV     #$00,TASC       ; start Timer 


LOOP    lda     TASC0
        bpl     LOOP
        bclr    7,TASC0         
        lda     PORTB           ; on PORTA 1 Khz          
        eor     #$FF
        sta     PORTB
*       ---------------
        lda     TACH0L
        add     #$CC            ; add 1228 decimal
        sta     TACH0L          ; hex 04 CC 
        lda     TACH0H
        adc     #$04
        sta     TACH0H
                
        lda     TACH0L          ; write again to low byte
        sta     TACH0L
*       ----------------

        jmp     LOOP


********* Reset vector *********************
        ORG     $FFFE
        dw      START

***  on PTE4 output compare with toggle 1 KHz  ***

Timer B COMPARE with TOGGLE OUTPUT 1KHz

TIMER B The compare function with output toggle is set

****************************************
** Register **
$include        'mr_regs.inc'

        ORG     $F000
START   RSP
        MOV     #$01,CONFIG
        MOV     #$FF,DDRB
        MOV     #$AA,PORTB
        MOV     #$30,TBSC       ; stop Timer to make changes
        MOV     #$14,TBSC0      ; compare with toggle 
        MOV     #$00,TBSC       ; start Timer 


LOOP    lda     TBSC0
        bpl     LOOP
        bclr    7,TBSC0         
        lda     PORTB           ; on PORTB 1 Khz          
        eor     #$FF
        sta     PORTB
*       ---------------
        lda     TBCH0L
        add     #$CC            ; add 1228 decimal
        sta     TBCH0L          ; hex 04 CC 
        lda     TBCH0H
        adc     #$04
        sta     TBCH0H
                
        lda     TBCH0L          ; write again to low byte
        sta     TBCH0L
*       ----------------

        jmp     LOOP


********* Reset vector *********************
        ORG     $FFFE
        dw      START

***  on PTE1 output compare with toggle 1 KHz  ***

Timer B INTERRUPT OUTPUT 1KHz

The same example with INTERRUPT routine

****************************************
** Register **
$include        'mr_regs.inc'


        ORG     $F000
START   RSP
        MOV     #$01,CONFIG
        MOV     #$30,TBSC       ; stop Timer to make changes
        MOV     #$54,TBSC0      ; compare with toggle + interrupt
        MOV     #$00,TBSC       ; start Timer
        CLI                     ; enable interrupt


LOOP        jmp     LOOP

****************************************
INT_TB_CH0
        bclr    7,TBSC0
        lda     TBCH0L
        add     #$CC            ; add 1228 decimal
        sta     TBCH0L          ; hex 04 CC
        lda     TBCH0H
        adc     #$04
        sta     TBCH0H

        lda     TBCH0L          ; write again to low byte
        sta     TBCH0L
        
        RTI        

********* Reset vector *********************
        
        ORG     $FFE2
        dw      INT_TB_CH0

        ORG     $FFFE
        dw      START


***  on PTE1 output compare with toggle 1 KHz  ***

Timer B TWO INTERRUPTS OUTPUT 1KHz and 3KHz

*TWO INTERRUPT routines

****************************************
** Register **
$include        'mr_regs.inc'


        ORG     $F000
START   RSP
        MOV     #$01,CONFIG
        MOV     #$30,TBSC       ; stop Timer to make changes
        MOV     #$54,TBSC0      ; compare with toggle + interrupt
        MOV     #$54,TBSC1      ; compare with toggle + interrupt
        ldhx    #$04CC
        sthx    TBCH0H
        ldhx    #$019A
        sthx    TBCH1H
        MOV     #$00,TBSC       ; start Timer
        CLI                     ; enable interrupt


LOOP        jmp     LOOP

****************************************
INT_TB_CH0
        bclr    7,TBSC0
        lda     TBCH0L
        add     #$CC            ; add 1228 decimal
        sta     TBCH0L          ; hex 04 CC
        lda     TBCH0H
        adc     #$04
        sta     TBCH0H

        lda     TBCH0L          ; write again to low byte
        sta     TBCH0L

        RTI

****************************************
INT_TB_CH1
        bclr    7,TBSC1
        lda     TBCH1L
        add     #$9A            ; add 
        sta     TBCH1L          ; hex 01 9A
        lda     TBCH1H
        adc     #$01
        sta     TBCH1H

        lda     TBCH1L          ; write again to low byte
        sta     TBCH1L

        RTI

********* Reset vector *********************

        ORG     $FFE0
        dw      INT_TB_CH1

        ORG     $FFE2
        dw      INT_TB_CH0

        ORG     $FFFE
        dw      START


***  on PTE1 output compare with toggle Freq: 1 KHz  ***
***  on PTE2 output compare with toggle Freq: 3 KHz  ***

PWM single output

$Include 'mr_regs.inc'

       org $8000

START  mov   #$91,CONFIG    ; EDGE=1, INDEP=1, COPD=1 (cop disabled)
       ldhx  #$100          ; Load Counter Modulo Register with 256T
       sthx  PMODH

       ldhx  #$20           ; PWM 25%
       sthx  PVAL1H

       mov   #0,PCTL2       ; Reload every PWM cycle, fastest PWM frequency
       mov   #3,PCTL1       ; no interrupt, load parameters, PWM on
       bset  1,PCTL1        ; force reload on PWM parameters
       mov   #$3F,PWMOUT

LOOP

       jmp LOOP

       ORG $FFFE
       dw   START             ; Reset Vector

PWM six outputs

RomStart     EQU  $8000         ; Valid Rom for MR32

$Include 'mr_regs.inc'

        org RomStart

START   rsp
        mov #$91,CONFIG     ; EDGE=1, INDEP=1, COPD=1 (cop disabled)
        ldhx  #256T        ; Load Counter Modulo Register with 256T
        sthx  pmodh

        ldhx  #0T           ; PWM 0/6
        sthx  pval1h

        ldhx  #43T          ; PWM 1/6
        sthx  pval2h

        ldhx  #85T          ; PWM 2/6
        sthx  pval3h

        ldhx  #128T         ; PWM 3/6
        sthx  pval4h

        ldhx  #171T         ; PWM 4/6
        sthx  pval5h

        ldhx  #213T         ; PWM 5/6
        sthx  pval6h

        mov   #00,PCTL2     ; Reload every PWM cycle, fastest PWM frequency
        mov   #03,PCTL1     ; no interrupt, load parameters, PWM on
        bset  1,PCTL1       ; force reload on PWM parameters
        mov   #$3F,pwmout

LOOP    inc   pval1l
        inc   pval2l
        inc   pval3l
        inc   pval4l
        inc   pval5l
        inc   pval6l
       
        bset  1,PCTL1        ; force reload on PWM parameters

        ldhx  #0
next_x  aix   #1
        cphx  #$800
        blo   next_x

        jmp   LOOP

        ORG  $FFFE
        dw   START    ; Reset Vector

PWM 6 outputs to drive a 3phase ac motor

RAMStart    EQU $0060
RomStart    EQU $8000
VectorStart EQU $FFD2

$Include 'mr_regs.inc'


        org RamStart

PTR_SINUS       ds 3
LOOPTIMING      ds 1
LOOPCOUNTER     ds 1
TEMP            ds 1
TIMER           ds 1


              org RomStart
;******** sine table with 192 base points
SINE_TABLE
 DB 128T,132T,136T,140T,145T,149T,153T,157T   ; line 1
 DB 161T,165T,169T,173T,177T,180T,184T,188T   ; line 2
 DB 192T,195T,199T,202T,205T,209T,212T,215T   ; line 3
 DB 218T,221T,223T,226T,229T,231T,234T,236T   ; line 4
 DB 238T,240T,242T,244T,245T,247T,248T,250T   ; line 5
 DB 251T,252T,253T,253T,254T,254T,255T,255T   ; line 6
 DB 255T,255T,255T,254T,254T,253T,253T,252T   ; line 7
 DB 251T,250T,248T,247T,245T,244T,242T,240T   ; line 8
 DB 238T,236T,234T,231T,229T,226T,223T,221T   ; line 9
 DB 218T,215T,212T,209T,205T,202T,199T,195T   ; line 10
 DB 191T,188T,184T,180T,177T,173T,169T,165T   ; line 11
 DB 161T,157T,153T,149T,145T,140T,136T,132T   ; line 12
 DB 128T,124T,120T,116T,111T,107T,103T,099T   ; line 13
 DB 095T,091T,087T,083T,079T,076T,072T,068T   ; line 14
 DB 064T,061T,057T,054T,051T,047T,044T,041T   ; line 15
 DB 038T,035T,033T,030T,027T,025T,022T,020T   ; line 16
 DB 018T,016T,014T,012T,011T,009T,008T,006T   ; line 17
 DB 005T,004T,003T,003T,002T,002T,001T,001T   ; line 18
 DB 001T,001T,001T,002T,002T,003T,003T,004T   ; line 19
 DB 005T,006T,008T,009T,011T,012T,014T,016T   ; line 20
 DB 018T,020T,022T,025T,027T,030T,033T,035T   ; line 21
 DB 038T,041T,044T,047T,051T,054T,057T,061T   ; line 22
 DB 065T,068T,072T,076T,079T,083T,087T,091T   ; line 23
 DB 095T,099T,103T,107T,111T,116T,120T,124T   ; line 24

;*****REPEAT TABLE*****
 DB 128T,132T,136T,140T,145T,149T,153T,157T   ; line 25
 DB 161T,165T,169T,173T,177T,180T,184T,188T   ; line 26
 DB 192T,195T,199T,202T,205T,209T,212T,215T   ; line 27
 DB 218T,221T,223T,226T,229T,231T,234T,236T   ; line 28
 DB 238T,240T,242T,244T,245T,247T,248T,250T   ; line 29
 DB 251T,252T,253T,253T,254T,254T,255T,255T   ; line 30
 DB 255T,255T,255T,254T,254T,253T,253T,252T   ; line 31
 DB 251T,250T,248T,247T,245T,244T,242T,240T   ; line 32
 DB 238T,236T,234T,231T,229T,226T,223T,221T   ; line 33
 DB 218T,215T,212T,209T,205T,202T,199T,195T   ; line 34
 DB 191T,188T,184T,180T,177T,173T,169T,165T   ; line 35
 DB 161T,157T,153T,149T,145T,140T,136T,132T   ; line 36
 DB 128T,124T,120T,116T,111T,107T,103T,099T   ; line 37
 DB 095T,091T,087T,083T,079T,076T,072T,068T   ; line 38
 DB 064T,061T,057T,054T,051T,047T,044T,041T   ; line 39
 DB 038T,035T,033T,030T,027T,025T,022T,020T   ; line 40
 DB 018T,016T,014T,012T,011T,009T,008T,006T   ; line 41
 DB 005T,004T,003T,003T,002T,002T,001T,001T   ; line 42
 DB 001T,001T,001T,002T,002T,003T,003T,004T   ; line 43
 DB 005T,006T,008T,009T,011T,012T,014T,016T   ; line 44
 DB 018T,020T,022T,025T,027T,030T,033T,035T   ; line 45
 DB 038T,041T,044T,047T,051T,054T,057T,061T   ; line 46
 DB 065T,068T,072T,076T,079T,083T,087T,091T   ; line 47
 DB 095T,099T,103T,107T,111T,116T,120T,124T   ; line 48

;*****REPEAT TABLE*****
 DB 128T,132T,136T,140T,145T,149T,153T,157T   ; line 25
 DB 161T,165T,169T,173T,177T,180T,184T,188T   ; line 26
 DB 192T,195T,199T,202T,205T,209T,212T,215T   ; line 27
 DB 218T,221T,223T,226T,229T,231T,234T,236T   ; line 28
 DB 238T,240T,242T,244T,245T,247T,248T,250T   ; line 29
 DB 251T,252T,253T,253T,254T,254T,255T,255T   ; line 30
 DB 255T,255T,255T,254T,254T,253T,253T,252T   ; line 31
 DB 251T,250T,248T,247T,245T,244T,242T,240T   ; line 32
 DB 238T,236T,234T,231T,229T,226T,223T,221T   ; line 33
 DB 218T,215T,212T,209T,205T,202T,199T,195T   ; line 34
 DB 191T,188T,184T,180T,177T,173T,169T,165T   ; line 35
 DB 161T,157T,153T,149T,145T,140T,136T,132T   ; line 36
 DB 128T,124T,120T,116T,111T,107T,103T,099T   ; line 37
 DB 095T,091T,087T,083T,079T,076T,072T,068T   ; line 38
 DB 064T,061T,057T,054T,051T,047T,044T,041T   ; line 39
 DB 038T,035T,033T,030T,027T,025T,022T,020T   ; line 40
 DB 018T,016T,014T,012T,011T,009T,008T,006T   ; line 41
 DB 005T,004T,003T,003T,002T,002T,001T,001T   ; line 42
 DB 001T,001T,001T,002T,002T,003T,003T,004T   ; line 43
 DB 005T,006T,008T,009T,011T,012T,014T,016T   ; line 44
 DB 018T,020T,022T,025T,027T,030T,033T,035T   ; line 45
 DB 038T,041T,044T,047T,051T,054T,057T,061T   ; line 46
 DB 065T,068T,072T,076T,079T,083T,087T,091T   ; line 47
 DB 095T,099T,103T,107T,111T,116T,120T,124T   ; line 48


                org $9000
**************************************************************
* DUMMY_ISR - Dummy Interrupt Service Routine. *
**************************************************************
dummy_isr       rti             ; interrupt return



Main_Init:      mov     #$01,CONFIG     ;INDEP=0, complementary output  COPD=0 (cop enabled)
;               ---------------
                bclr    5,PCTL          ; set PLL activ
                lda     #$33
                sta     PPG
                bset    5,PCTL
                bset    4,PCTL
;               ----------------------- set Stack Pointer
                ldhx    #$02FF
                txs
;--------------------------------- clear RAM ------------
                clr     TEMP
                ldhx    #RamStart
next_x          mov     TEMP,X+
                cphx    #$0300
                blo     next_x
;---------------------------------------
                bset    3,DDRB                  ; only for test to see interrupt time
                bset    6,DDRB                  ; only for test to see loop time
                jsr     Init_PWMMC
                cli                             ; Allow interrupts to happen
*************************************************************
**************************************************************
LOOP            sta    $FFFF                    ;   reset watchdog if cop enabled
                brclr 7,LOOPTIMING,LOOP         ;   Realtime approx. 5 msec
                bclr  7,LOOPTIMING
* -----
                dec     LOOPCOUNTER
                bne     LoopCountOkay

                lda     PORTB
                and     #%01000000
                beq     set_6
                bclr    6,PORTB
                bra     ok_6
set_6           bset    6,PORTB
ok_6
                mov     #200T,LOOPCOUNTER
LoopCountOkay
                jmp LOOP


**************************************************************
* Init_PWM for 3 phase sine output
**************************************************************
Init_PWMMC      ldhx  #256T           ; Load Counter Modulo Register with 256T
                sthx   pmodh
                mov    #0T,DEADTM

                ldhx   #$8000
                sthx   PTR_SINUS

                ldhx   #20T
                sthx   PVAL1H

                ldhx   #40T
                sthx   PVAL3H

                ldhx   #80T
                sthx   PVAL5H

                mov   #0,PCTL2           ; Reload every PWM cycle, fastest PWM frequency
                mov   #$23,PCTL1         ; interrupt, load parameters, PWM on
                bset  1,PCTL1            ; force reload on PWM parameters
                mov   #%00111111,pwmout
                rts
***********************************************************

INT_PWM6        pshh
                lda      PCTL1
                bclr     4,PCTL1

                ldhx     PTR_SINUS
                lda      0,X            ; indexed H:X with offset
                sta      PVAL1L

                lda     64T,X
                sta     PVAL3L

                lda     128T,X
                sta     PVAL5L

                bset    1,PCTL1

                inc     PTR_SINUS+2
                bne     ptr_ok
                lda     PTR_SINUS+1
                inca
                cmp     #192T
                blo     save_a
                clra
save_a          sta     PTR_SINUS+1
ptr_ok
****************************************
                dec     TIMER
                bne     Timer_Okay
                mov     #$FF,LOOPTIMING
                mov     #$24,TIMER
Timer_Okay
*****************************************
                lda PORTB
                eor #%00001000
                sta PORTB

                pulh
                rti


**************************************************************
* Vectors - Timer Interrupt Service Routine.                 *
**************************************************************
   org  VectorStart

 dw  dummy_isr    ; SCI Transmit Vector
 dw  dummy_isr    ; SCI Receive Vector
 dw  dummy_isr    ; SCI Error Vector
 dw  dummy_isr    ; SPI Transmit Vector
 dw  dummy_isr    ; SPI Receive Vector
 dw  dummy_isr    ; ADC Conversion Complete
 dw  dummy_isr    ; TIM2 Overflow Vector
 dw  dummy_isr    ; TIM2 Channel 1 Vector
 dw  dummy_isr    ; TIM2 Channel 0 Vector
 dw  dummy_isr    ; TIM1 Overflow Vector
 dw  dummy_isr    ; TIM1 Channel 3 Vector  PE7
 dw  dummy_isr    ; TIM1 Channel 2 Vector
 dw  dummy_isr    ; TIM1 Channel 1 Vector
 dw  dummy_isr    ; TIM1 Channel 0 Vector
 dw  INT_PWM6     ; PWMMC Vector
 dw  dummy_isr    ; Fault 4 Vector
 dw  dummy_isr    ; Fault 3 Vector
 dw  dummy_isr    ; Fault 2 Vector
 dw  dummy_isr    ; Fault 1 Vector
 dw  dummy_isr    ; PLL Vector
 dw  dummy_isr    ; ~IRQ1 Vector
 dw  dummy_isr    ; SWI Vector
 dw  main_init    ; Reset Vector

PWM six outputs 3phase with delaytime

under construction

PWM 3phase analog controls frequency out

under construction

PWM H-bridge control

under construction

Read analog channel

$include 'mr_regs.inc'

                ORG     $8000

START           mov     #$91,CONFIG     ; disable COP
                mov     #$FF,DDRA       ;PORTA all outputs 
                mov     #0,DDRB
                mov     #$FF,DDRE       ;PORTE all outputs 

                mov     #$70,ADCLK     ; 8 Bit Modus

LOOP            lda     #0
                sta     ADSCR

                ldhx    #$1000
next_delay      aix     #-1
                cphx    #$0
                bne     next_delay

                ldhx    ADRH
                stx     PORTA

                lda     PORTE
                eor     #$FF
                sta     PORTE

                JMP     LOOP

                ORG     $FFFE
                dw      START      ; Reset vector

Read analog and send byte over RS232

$include 'mr_regs.inc'

                ORG     $8000

START           mov     #$91,CONFIG     ; disable COP
                mov     #$55,PORTA
                mov     #$FF,DDRA
                mov     #0,DDRB
                mov     #$FF,DDRE

                mov     #$70,ADCLK     ; 8 Bit Modus

                mov     #$02,SCBR       ;  Baudrate 9600
                mov     #$40,SCC1
                mov     #$0C,SCC2       ; RX and TX enabled
                                        ; only TX is in use
LOOP            lda     #0
                sta     ADSCR

                ldhx    #$1000
next_delay      aix     #-1
                cphx    #$0
                bne     next_delay

                ldhx    ADRH
                stx     PORTA

                lda     SCS1  ; read first status register
                stx     SCDR            ; send byte

                lda     PORTE
                eor     #$FF
                sta     PORTE

                JMP     LOOP

                ORG     $FFFE
                dw      START           ; Reset vector

5 RS232 see byte on PORTB

RomStart     EQU  $8000         ; Valid Rom for MR32
VectorStart  EQU  $FFD2

$Include 'mr_regs.inc'

                ORG RomStart
START:          mov #$91,CONFIG        ; EDGE=1, INDEP=1, COPD=1 (cop disabled)
                rsp                    ; reset stack pointer

;               mov     #1,SCBR        ; 19200 Baud
                mov     #2,SCBR        ; 9600 Baud
                mov     #$40,SCC1      ; set BIT5 to enable the SCI
                mov     #$0C,SCC2      ; receiver and transmitter enabled

LOOP            jsr    CHECK_RS232
                jmp    LOOP

;================================================
CHECK_RS232     brclr  5,SCS1,EXIT_RS232
                mov   #$FF,DDRB         ; set PORTB all outputs
                lda   SCDR
                sta   PORTB             ; view RS232 BYTE on PORTB
                sta   SCDR              ; send received Byte
EXIT_RS232      rts

                ORG $FFFE
                dw  START

RS232 send a text

RamStart     EQU  $0060
RomStart     EQU  $8000         ; Valid Rom for MR32

$Include 'mr_regs.inc'

                ORG     RamStart
TEMP   ds  1

                ORG     RomStart
START:          mov     #$91,CONFIG        ; EDGE=1, INDEP=1, COPD=1 (cop disabled)
                rsp                    ; reset stack pointer

;               mov     #1,SCBR        ; 19200 Baud
                mov     #2,SCBR        ; 9600 Baud
                mov     #$40,SCC1      ; set BIT5 to enable the SCI
                mov     #$0C,SCC2      ; receiver and transmitter enabled

LOOP            jsr    CHECK_RS232
                jmp    LOOP

CHECK_RS232     brclr  5,SCS1,EXIT_RS232
                mov   #$FF,DDRB         ; set PORTB all outputs
                lda   SCDR
                cmp   #'T'
                beq   SEND_TEXT
                sta   PORTB             ; view RS232 BYTE on PORTB
                sta   SCDR              ; send received Byte
EXIT_RS232      rts

SEND_TEXT       ldhx    #TEXT1
NEXT_BYTE       mov     X+,TEMP       ; Variable TEMP
                lda     TEMP
                beq     EXIT_SEND
                sta     SCDR
WAIT            brclr   7,SCS1,WAIT
                bra     NEXT_BYTE
EXIT_SEND       rts

TEXT1  db  $0D,$0A
       db  'Hello from serial interface'
       db  $0D,$0A,$00


               ORG $FFFE
               dw  START

RS232 send analog as hex

under construction

RS232 send analog as ASCII

under construction

Read SINE-TABLE and send byte over RS232

$include        'mr_regs.inc'

                org $80
PTR1            ds 2

                ORG    $8000

Sintab          DB     128T,177T,217T,245T,255T,245T,217T,177T,128T
                DB     79T,39T,11T,1T,11T,39T,79T

Start           mov     #$91,Config
                rsp
                mov     #0,PORTA
                mov     #$FF,DDRA
                ldhx    #Sintab
                sthx    PTR1

                mov     #$02,SCBR       ;  Baudrate 9600
                mov     #$40,SCC1
                mov     #$0C,SCC2       ; RX and TX enabled
                                        ; only TX is in use
Loop            ldhx    PTR1
                mov     X+,PortA
                cphx    #Sintab+16T
                blo     save_ptr1
                ldhx    #SINTAB
save_ptr1       sthx    PTR1

                lda     PORTA
                ldx     SCS1  ; read first status register
                sta     SCDR            ; send byte

                jsr     DELAY

                jmp     LOOP

DELAY           ldhx    #$F000
next_delay      aix     #-1
                cphx    #0
                bne     next_delay
                rts

                org     $FFFE
                dw      Start

LCD control 4 Bit databus

$Include 'mr_regs.inc'

                org  $8000

START           mov     #$91,CONFIG     ; EDGE=1, INDEP=1, COPD=1 (cop disabled)
                rsp
                mov     #$00,PORTB
                mov     #$3F,DDRB

                lda     #$03
                jsr     LcdInstr1
                lda     #$03
                jsr     LcdInstr1
                lda     #$03
                jsr     LcdInstr1
                                     ;                  x  x  x  DL N  F  x  x
                lda     #%00101000   ; 28 Function Set: 0  0  1  0  1  0  0  0
                jsr     LcdInstr2    ; DL: 0=4-Bit-Interface  1=8-Bit-Interface

                lda     #%00001100   ;0C
                jsr     LcdInstr2
                                       ;               x  x  x  x  x  x  ID S
                lda     #%00000110     ;06 Entry Mode: 0  0  0  0  0  1  1  0
                jsr     LcdInstr2      ; ID : 0=Adress decrement 1=Adress Increment

                lda    #$80            ; set cursor to home position
                jsr     LcdInstr2

                lda     #'O'           ; write OKAY to LCD
                jsr     WriteLcdData
                lda     #'K'
                jsr     WriteLcdData
                lda     #'A'
                jsr     WriteLcdData
                lda     #'Y'
                jsr     WriteLcdData

LOOP            jmp     LOOP

******************** LCD UTIL ***************************
LcdInstr2       psha
                lsra
                lsra
                lsra
                lsra
                sta     PORTB
                bclr    5,PORTB
                bset    4,PORTB
                bclr    4,PORTB
                pula
LcdInstr1       and     #$0F
                sta     PORTB
                bclr    5,PORTB
                bset    4,PORTB
                bclr    4,PORTB
                jsr     Delay
                rts
;               ----
WriteLcdData    psha
                lsra
                lsra
                lsra
                lsra
                sta     PORTB
                bset    5,PORTB
                bset    4,PORTB
                bclr    4,PORTB
                pula
                and     #$0F
                sta     PORTB
                bset    5,PORTB
                bset    4,PORTB
                bclr    4,PORTB
                jsr     Delay
                rts

Delay           ldhx    #$2000
next_x          aix     #-1
                cphx    #0
                bne     next_x
                rts

                ORG    $FFFE
                dw     START

LCD analog value on PB7 to LCD binary to ASCII conversion

$Include 'mr_regs.inc'

                org $60
ADC_WERT        DS      1
LCDBUF1         DS      1
LCDBUF2         DS      1
LCDBUF3         DS      1

                 org    $8000

START           mov    #$91,CONFIG     ; EDGE=1, INDEP=1, COPD=1 (cop disabled)
                rsp                    ; reset stack pointer
                mov    #0,PORTB
                mov    #$3F,DDRB

                lda     #$03
                jsr     LcdInstr1
                lda     #$03
                jsr     LcdInstr1
                lda     #$03
                jsr     LcdInstr1
                                     ;                  x  x  x  DL N  F  x  x
                lda     #%00101000   ; 28 Function Set: 0  0  1  0  1  0  0  0
                jsr     LcdInstr2    ; DL: 0=4-Bit-Interface  1=8-Bit-Interface

                lda     #%00001100   ;0C
                jsr     LcdInstr2
                                       ;               x  x  x  x  x  x  ID S
                lda     #%00000110     ;06 Entry Mode: 0  0  0  0  0  1  1  0
                jsr     LcdInstr2      ; ID : 0=Adress decrement 1=Adress Increment

                lda    #$80            ; Set cursor to HOME
                jsr     LcdInstr2
                lda     #'L'
                jsr     WriteLcdData
                lda     #'C'
                jsr     WriteLcdData
                lda     #'D'
                jsr     WriteLcdData

                mov     #$70,ADCLK   ; 8 Bit conversion

LOOP            lda     #7
                sta     ADSCR
                jsr     Delay
                ldhx    ADRH
                stx     ADC_WERT
                jsr     BINASCII
                jsr     LCDOUT

                jmp     LOOP

BINASCII        mov     #$30,LCDBUF1
                mov     #$30,LCDBUF2
                mov     #$30,LCDBUF3
                lda     ADC_WERT
CHECK_100       cmp     #100T
                blo     CHECK_10
                sub     #100T
                inc     LCDBUF1
                bra     CHECK_100
CHECK_10        cmp     #10T
                blo     CHECK_1
                sub     #10T
                inc     LCDBUF2
                bra     CHECK_10
CHECK_1         add     LCDBUF3
                sta     LCDBUF3
                rts

LCDOUT          lda     #$85      ; set cursor first line position 5
                jsr     LcdInstr2
                lda     LCDBUF1
                jsr     WriteLcdData
                lda     LCDBUF2
                jsr     WriteLcdData
                lda     LCDBUF3
                jsr     WriteLcdData
                rts

******************** LCD UTIL ***************************
LcdInstr2       psha
                lsra
                lsra
                lsra
                lsra
                sta     PORTB
                bclr    5,PORTB
                bset    4,PORTB
                bclr    4,PORTB
                pula
LcdInstr1       and     #$0F
                sta     PORTB
                bclr    5,PORTB
                bset    4,PORTB
                bclr    4,PORTB
                jsr     Delay
                rts
;               ----
WriteLcdData    psha            ; save A -> stack
                lsra
                lsra
                lsra
                lsra
                sta     PORTB
                bset    5,PORTB
                bset    4,PORTB
                bclr    4,PORTB
                pula            ; load A from stack
                and     #$0F
                sta     PORTB
                bset    5,PORTB
                bset    4,PORTB
                bclr    4,PORTB
                jsr     Delay
                rts

Delay           ldhx    #$2000
next_x          aix     #-1
                cphx    #0
                bne     next_x
                rts

                ORG    $FFFE
                dw     START

7 Chipcard read

under construction

8 Stepper Control

under construction

9 Infrared RC5 code out

under construction